The disclosure relates generally to a method and an apparatus for buffering analog information output by a capture element.
A known integrated circuit (IC) with a capture array employs an analog to digital (ADC) converter to convert the analog information captured by the capture array into digital data. The digital data is buffered in a digital memory. The output rate of the IC depends on the speed of the ADC converter. The digital data may be further processed before it is output through a serial or parallel output interface.
FIG. 1 illustrates an example of a known pixel logic circuit 100 that employs a capture element 102 and multiple switches 104, 106, and 108 arranged to reset, amplify and read the analog, or pixel, information from capture element 102. The read analog information passes through a column amplifier 110 and an ADC 112 before it is available as a digital pixel output 114. Capture element 102 may be one of multiple multiplexed pixels of an imaging sensor.
FIG. 2 illustrates a timing diagram 200 for capture element 102. Timing diagram 200 illustrates that after a reset time Trst, an integration time Tint begins. During Tint, capture element 102 collects electromagnetic radiation. The length of Tint determines the aperture of capture element 102. Subsequently, at Ts, a sample is read from capture element 102, which is subsequently converted to digital pixel output 114 during Tadc. Ttotal represents the time required to convert electromagnetic radiation to digital pixel values. Rows 1 and 2 of timing diagram 200 illustrate an example of a rolling shutter, where the Tadc periods follow one another and the samples are taken according to the desired aperture such that all the samples have the same integration time, e.g. the same aperture length. In a global shutter arrangement, the capture elements are reset at the same time and the aperture lengths vary depending on for how long the analog information is captured by the capture elements. A complementary metal oxide semiconductor (CMOS) image sensor typically uses a rolling shutter while a charge coupled device (CCD) typically uses a global shutter. The CCD shifts the pixel information substantially simultaneously to adjacent elements, from which the pixel information is obtained. Subsequent frames of pixel information cannot be obtained until the prior information has been read, therefore the ADC remains the bottleneck.
FIG. 3 illustrates a known imaging sensor circuit 300 comprising a pixel array 302. Column amplifiers 110, a row decoder 320, a column multiplexer 322 and control logic 324 read out the analog information from pixel array 302 through ADC 112. Digital pixel output 114 typically has a frame rate equal to display rates at which video appears normal, which may be referred to as the normal speed display rate. Digital pixel output 114 is stored in a random access memory (RAM) buffer 306. An in-process image 308 is compiled in buffer 306 as the pixel information is converted.
It is also known to combine multiple images in a high dynamic range (HDR) image. Multiple images of a common scene can be obtained with multiple image sensor arrays. However, the optical centers and the view angles of the image sensor arrays will differ. In another known approach, multiple images taken at different points in time are combined. In both cases, the resulting HDR images suffer loss of detail due to the spatial or the temporal, or motion, disparities between the images. The complexity of the HDR image combination process is increased to compensate, to the extent possible, for the disparities.
A need exists for methods and apparatus to decouple the rate at which analog information is captured from the rate at which the analog information is converted to digital data.